With the increasing array density of successive generations of memory chips, it is desirable to incorporate and merge other functions, and thus other devices, onto the memory chips. Many times, however, memory chips incorporating other functions and technologies require additional processing steps to incorporate the other functions on a single chip and, thus, are not cost competitive as compared to the alternative of combining separate chips at the card or package level wherein each is being produced with independently optimized technologies.
For example, mixed-mode signal processing, radio-frequency (RF) signal processing, and system-on-chip (SoC) semiconductor applications often involve integrating capacitors on memory chips. Integrating capacitors onto chips with other semiconductor devices, such as DRAMs, must be performed by adding no or few additional process steps during fabrication in order to keep the devices cost competitive.
One example of a conventional integrated capacitor is shown in FIG. 1, which illustrates a cross-section view of a semiconductor wafer 100 comprising a logic area, a dynamic random access memory (DRAM) area, and a mixed-mode capacitor area. In this case, the mixed-mode capacitor area includes a polysilicon-insulator-polysilicon (PIP) capacitor 116. As is known in the art, a bottom electrode 118 of the PIP capacitor 116 comprises a layer of doped polysilicon, which is typically formed in the same process steps as the polysilicon gate electrodes for the transistors contained in the DRAM area and the logic area. A dielectric layer 120 is formed over the bottom electrode 118, and a top electrode 122 of a doped polysilicon is formed over the dielectric layer. Contact is made to the bottom electrode 118 and the top electrode 122 by vias 124, which are generally filled with copper, tungsten, or the like. As one of ordinary skill in the art will appreciate, this process requires extra processing steps, such as forming the dielectric layer 120 and the top electrode 122, to complete the fabrication of the PIP capacitor. Furthermore, the dielectric layer 120 may easily become damaged during the etching process to form the top electrode 122 and spacers. PIP capacitors formed in this manner are typically characterized by lower capacitance and lower conductance, which limits its applicability in high-speed applications and smaller designs.
FIG. 2a illustrates a cross-section view of a semiconductor wafer 200 having an integrated metal-insulator-metal (MIM) capacitor 208. MIM capacitors are generally more desirable because they provide depletion-free, high conductance electrodes suitable for high speed applications at a lower cost. MIM capacitors also provide scalable storage node capacitors for embedded DRAM designs. Generally, as illustrated in FIG. 2a, the MIM capacitor 208 comprises a metal bottom electrode 210 and a metal top electrode 212 with a stop layer 214 positioned between the bottom electrode 210 and the top electrode 212. The stop layer 214, typically a back-end-of-line stop layer (BEOL) such as Si3N4, SiC, or the like, acts as the dielectric insulator between the bottom electrode 210 and the top electrode 212. A MIM design such as this requires additional masks and process steps to form the MIM capacitor. Furthermore, the use of the stop layer 214 as the dielectric induces leakage between the top electrode and the bottom electrode, and the MIM capacitor has a tendency to breakdown at the corners of the bottom electrode 210 due to the electric field intensity at these regions.
FIG. 2b is a cross-section view of wafer 250 illustrating another type of a MIM capacitor 252. The MIM capacitor 252 of FIG. 2b is similar to the MIM capacitor 208 of FIG. 2a, except that the insulating layer between bottom electrode 254 and top electrode 256 is a dielectric layer 258, such as an oxide, rather than the stop layer 214 (FIG. 2a). Again, however, the MIM capacitor 252 of FIG. 2b requires additional masks and processing steps to fabricate. Additionally, the process is not easily integrated with a high-K dielectric required for a high capacitance design. The dielectric layer is also easily damaged during the etching process used to form the top electrode.
Thus, there is a need for an integrated capacitor compatible with the standard semiconductor processes.